The present invention relates, in general, to a method of providing isolation for MOS circuits, and more particularly, to a method of providing deep isolation trenches having oxidized side walls and filled with heavily doped polysilicon wherein the work function of the doped polysilicon prevents inversion of the charges on the trench side wall and the consequent formation of parasitic transistors.
In monolithic integrated circuit technology, it is usually necessary to isolate various active and passive elements from one another in the integrated circuit structure. A variety of techniques are known for providing such isolation, with one form involving the formation of grooves or depressions in silicon around the regions to be isolated. During the groove formation, the remainder of the silicon surface is covered by a protective film which is substantially unaffected by the etching process used to form the grooves. Thereafter, the silicon in the groove area is oxidized with the resulting silicon dioxide filling the groove as well as oxidizing further into the silicon. However, one of the major problems with this process is the formation of what is known as "birds beak", which is a non-planar silicon dioxide formation at the top periphery of the groove, caused by lateral oxidation underneath the protective film provided during the etching process. The consequence of this lateral oxidation is a general stress in the perimeter region of the groove as well as difficulties in achieving good diffusions abutting the vertical portion of the silicon dioxide, thereby defeating to some extent a major benefit of the original purpose of the silicon dioxide region. Although attempts have been made in the past to overcome the problems with this process, they have not been totally successful.
There has recently been a revival of interest in developing new integrated circuit isolation techniques because of the intensifying need to scale integrated circuits to smaller dimensions and the difficulty which has been encountered in similarly reducing the dimensions of the isolating devices formed by prior techniques. In particular, CMOS (complementary metal oxide semiconductor) technology has been difficult to scale because it is particularly susceptible to latchup, wherein adjacent transistors in an integrated circuit produce a large current flow which can cause permanent damage to CMOS circuits. Because of this susceptibility, due to poor isolation between adjacent elements, CMOS technology generally requires large p-channel to n-channel spacing.
Trench isolation has been proposed as a replacement for isolation by local oxidation in CMOS devices. One advantage of trench techniques is that they do not generate a "birds beak", and can thus produce isolation regions whose minimum dimensions are determined only by the lithographic feature size. Another advantage is that trenches might not require additional doping to control threshold voltages of parasitic devices. A key problem which has thus far prevented effective implementation of trench isolation in CMOS circuits, however, is the existence of oxide charges on the trench side walls. Such charges are inevitable in any oxidation, and trench side walls are particularly susceptible because of poor surface quality after the trench etching step and because they are usually [110] crystalline surfaces. The oxide charge is sufficient to invert typical P-type silicon in which the trench is formed, thereby electrically connecting separate n-type devices in the integrated circuit. The oxide charge has been measured to be 2E11/CM.sup.2 and it was found that to achieve device isolation in such a situation, it was necessary to keep n-type source/drain regions in the integrated circuit at least 1.5 microns away from the trenches. Such a large spacing is impractical for high density circuits.
Trenches have been used in integrated circuits for a variety of purposes, including increasing storage node capacitance in DRAMs (dynamic random access memory), but such trenches are not used for isolation. DRAM trenches have been filled with a conductive material which is contacted electrically at the top. This contact provides control over the potential of the conductor in the trench so that the conductor can serve as a capacitor plate. In this arrangement, a voltage can be applied to keep the trench side wall at a potential which prevents conduction from adjacent devices. However, the necessity of providing contacts at the top of the trenches makes circuit layout very difficult and substantially lowers the circuit packing density.
Trench structures have been proposed for providing contact with the substrate on which the integrated circuit is formed in bipolar and MOS circuits. Such structures have consisted of a trench in the center of an oxide isolation layer which was grown either before or after formation of the trench. The trench was filled with a conducting material such as doped polysilicon and contact was made between the conductor and the substrate by removal, as by reactive ion etching, of the oxide on the trench bottom prior to deposition of the conductor material in the trench. However, such a structure is not directly useful for high density isolation, since it uses local oxidation on the trench walls for the primary isolation.
Attempts have been made to dope the side walls of trenches to provide isolation, but such doping is extremely difficult and the use of typical diffusion sources for this purpose is, therefore, unlikely to give sufficient control over parasitic side wall threshold to permit the use of doping as a technique for device isolation.